The present invention relates, in general, to cell-based integrated circuits such as standard cells, and in particular, to an improved standard cell architecture to achieve high density and improved power distribution.
Standard cell design technology has been developed as a method of quickly and efficiently designing integrated circuits. Standard cell technology is characterized by its fixed set of predesigned basic cells, which are preferably configured for dense placement and efficient signal routing. Typically, these basic cells are placed on the integrated circuit in an array pattern with rows and columns and are interconnected by conductive traces to form more complex logic structures.
To aid the designer, pre-designed circuit units generally known as “macro cells” comprising one or more basic cells are provided in libraries. Macro cells include commonly used elements such as NAND gates, NOR gates, and flip-flops. These libraries may also include macro cells specially designed for a particular task. A designer selects desired elements from the library of macro cells and places them in a design. The macro cells may then be further interconnected with other elements in a variety of ways to perform desired functions. By selecting macro cells from a library and placing them into a design, a designer can quickly design complex functions without having to worry about the details of each individual transistor. Typically, a library of macro cells is designed for a certain IC manufacturing technology, and their design characteristics are fixed for that technology.
One of the design tradeoffs in a macro cell library is the height of the basic cells. Standard cell sizes ranging in height from 7 to 15 tracks or more have been provided in previous standard cell architectures. As a general rule, a smaller cell height results in a higher gate density and hence a lower cost, but a small height cell has a small transistor that may not be able to deliver sufficient current for high-speed applications. So, standard cell architectures have typically provided standard cell sizes that are relatively large (10–12 tracks high) in order to handle those applications that require higher current. Unfortunately, these large cells sizes are inefficient for many specific instances in which the macro cells do not need the extra current generated by larger transistors.
To combat this problem, a technique has been developed in which two basic cells are stacked together to make a single large double high cell for those macro cells in which larger transistors are needed. However, this technique introduced additional routing problems because of interconnections between the top and bottom stacked cells. The power rails (VDD and VSS) were routed horizontally through the cell on first level metal and, as a result, the second metal layer was used to make vertical connections between the top and the bottom halves of the stacked cell. In a three metal layer design, the second metal layer is important for global routing of signals and for accessing the input and output terminals inside of a cell. Consequently, these conventional dual-height cells resulted in designs with low area efficiency and have therefore not been popular.